1. Field of the Invention
The present invention relates generally to computer systems and, more particularly, to computer systems with L2 cache memory devices having memory controllers devoid of built-in L2 cache controller logic.
2. Description of the Related Art
Most modern computer systems include a processor and a main memory. Typically, the processor operates at a substantially faster speed than the main memory. Thus, the speed at which the processor decodes and executes instructions depends upon the rate at which the instructions can be transferred from the main memory to the processor. To reduce the time required for the processor to obtain instructions from the memory, many computer systems include a cache memory between the processor and the main memory.
A cache memory comprises a relatively small, yet relatively fast memory device arranged in close physical proximity to a processor. The cache memory is used to temporarily hold portions of the contents of the main memory which will be used in the near future by the processor. If these portions are not used within a predetermined amount of time, they are discarded. Before discarding the data, however, the system ascertains that the data is not the only latest copy of the data in main memory. If it is, the data is first copied into the main memory before it is discarded.
The cache memory usually stores many blocks of one or more words of data. To facilitate the retrieval of data, each block of data has associated with it an address tag that uniquely identifies the block in main memory of which it is a copy. As a result of the cache memory's close proximity to the processor as well as its speed, information in the cache memory is accessed faster than information in main memory. Hence, the processor spends far less time waiting for instructions stored in cache memory than in main memory.
In addition to using the cache memory to retrieve data from the main memory, the processor may also write data into the cache memory instead of directly to the main memory. When the processor desires to write data to the memory, the cache memory makes an address tag comparison to see if the data block into which data is to be written resides in the cache memory. If the data block exists in the cache memory, the data is written into the data block in the cache memory. If the data does not exist in the cache memory, the data may either be fetched into the cache memory and be updated or the data may be written directly into the main memory. Data written into the cache memory becomes the latest copy of the data and is usually referred to as a modified cache line.
In some applications, a second look aside cache memory (or L2 cache) may be added to the system. Ordinarily, the first cache (or L1 cache) is incorporated into the processor and the L2 cache is connected to the system bus between the processor and the main memory. As mentioned before, the L2 cache memory has a subset of the data in main memory. Similarly, the L1 cache memory has a subset of the data in the main memory. Further as described above, data may be written into the L1 cache if the data block incorporating the data resides in the L1 cache or into the L2 cache if the data block is stored therein. It is possible, therefore, for the L1 cache memory and the L2 cache memory to both contain modified copies, albeit different, of the same data.
Thus, it is necessary that the latest copy of the data be used by the system to ensure memory coherency. One known method of providing the necessary memory coherency is to implement a snooping bus protocol whereby a bus interface or other component in the system monitors the system bus for bus activity involving addresses of data items that are currently stored in the cache memory devices. For example, a memory controller with a built-in cache controller logic may look at a tag match signal and a modified line signal to ascertain the locality of the latest copy of a data.
Computer systems which support stand alone integrated L2 cache memory devices often do not have memory controllers with a built-in cache controller logic. The memory controllers of these systems have to query or snoop memory addresses referencing particular data to ascertain the location of the data's latest copy. In the prior art, when both the L1 and the L2 cache memory devices had a modified cache line which was being snooped and the processor was too busy to check the L1 cache memory device to see whether the line being snooped was a modified cache line, both copies of the data were transferred to the memory controller. The copy in the L2 cache was transferred in response to the original snoop and the copy in the L1 cache in response to a second snoop. As modified copies of data in the L1 cache are considered the most recent copies of the data, the transmitted copies from the L1 cache were always used and the transmitted data from the L2 cache discarded. If only the L2 cache contains a modified copy of the data, then a second snoop was still initiated to ascertain that the L1 cache did not have a modified cache line. Transmitting modified copies of data in both the L1 cache and the L2 cache when both devices contain a modified line as well as snooping the address twice when only the L2 cache has a modified cache line contribute to a decrease in the performance of the computer system.
Thus, there is a need in the art for a memory controller devoid of a built-in L2 controller logic to snoop a data address only once when a modified copy of the data resides only in an L2 cache and to induce transmission of only the modified copy of the data in an L1 cache when both the L1 cache and an L2 cache contain a modified copy of the data.